FPGA Implementation of Cyclic Code Encoder and Decoder

This paper presents Cyclic code Encoder and Decoder with its soft core design as well hardware implementation on FPGA. The design includes both encoder and decoder part that can be used in a communication system for encoding a message at the transmitter and decoding it, detecting error and correcting it on the receiver part. The source code for Encoder and Decoder has been formulated in VHDL ( VHSIC Hardware Description Language) and simulated and synthesized using Xilinx ISE14.3 The hardware implementation has been done on Xilinx Spartan6 LX45 FPGA.